The present invention relates to the field of a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) controller and particularly to a DDR controller, a method for implementing the same and a chip.
A design of a DDR SDRAM controller (simply referred to as a “DDR controller” in the document of this application) shall support the most essential and common commands of a DDR device, including ACTIVE (ACTIVE command), READ (READ command), WRITE (WRITE command) and PRECHARGE (PRECHARGE command), where ACTIVE and PRECHARGE incur an extra bandwidth consumption as a crucial factor influencing the bandwidth of the DDR device. Reference is made to FIG. 1 illustrating a general DDR transmission timing diagram. A storage unit internal to the DDR device is a matrix unit composed of Banks (blocks), rows and columns, and thus in order to access a storage cell selected by a row and a column in a bank, firstly an ACTIVE command is transmitted to activate the bank and the row, and then a READ/WRITE command is transmitted along with the column to be accessed, and the DDR transmits corresponding data onto a DQ (data line) port only after corresponding time parameters are satisfied. If there is a further second READ/WRITE command following the first READ/WRITE command, then the DDR controller may perform a process in the following three scenarios dependent upon a different bank and row to be accessed by the command:
(1) The second command accesses the same bank and row as the first command, and then the READ/WRITE command can be transmitted directly, as illustrated in FIG. 2.
(2) The second command accesses a bank same as that accessed by the first command and a row different from that accessed by the first command, then the row accessed by the first command is firstly disabled by a PRECHARGE command, then the row accessed by the second command is activated by an ACTIVE command, and finally the READ/WRITE command can be transmitted, as illustrated in FIG. 3.
(3) The second command accesses a different bank and a row from the first command, then firstly the bank and the row accessed by the second command is activated by an ACTIVE command, and then the READ/WRITE command is transmitted. A difference from the scenario in FIG. 2 lies in the absence of a PRECHARGE command, as illustrated in FIG. 4.
As can be apparent from the second and third scenarios, the data on DQ is no longer consecutive due to the insertion of the extra PRECHARGE and ACTIVE commands, thus resulting in a bandwidth waste. The DDR controller is typically designed to perform commands serially, that is, to parse a succeeding command only after a preceding command is completed, thus resulting in a bandwidth waste.